Here in Erlangen, we run several multiprocessors. One of them is a Convex SPP 1000 (eight PA-RISC/HP7100@100MHz per node, six nodes). Frank Bellosa (a member of the ELiTE project) decided to use the QuickThreads package as a base for further work. At this time, the QuickThreads package was not available for the PA-RISC architecture. If you want to know more about user-level thread concepts, in particular the QuickThreads and especially the porting to PA-RISC, click here (paper in german language).
To implement efficient preemption for user-level threads, I am currently working on directly exported timer interrupts. The work is done on a Mach 3.0 based OS. If preemption is build with standard UN*X-server mechanisms, setitimer() (or something like that) is used. Deep in the kernel timers are stored in the timer queue. Filling the timer queue is a lot of work for the server. When a timer expires, the softclock thread wakes up and calls the server. The server reloads the timer (if requested) and generates a signal (signal handling is very complicated with Mach) - once more, work for the server. If a thread private time is used, things are getting from bad to worse.
In this approach, expired timers are recognized within the timer interrupt. If one is found, the return address from kernel is changed to point to a handler in user space. In the most simplest case (direct return from interrupt), we have nearly no overhead with the drawback of getting minimal information from the kernel. If we want to get more information out from the microkernel we need to push data to the user's stack. Since this operation might block, we cannot do this directly from interrupt. Currently an AST (asynchronous software trap) is requested, and the job is carried out there. The described mechanism to signal an expired timer is called Up-Return. The whole concept ignores the presence of the server.
Here are the results of a simple benchmark. You can see, that this approach is more than 100 times faster than the conventional one.
| Cost of a single timer interruption on a HP715/33 workstation running a Mach 3.0 based OS | msec | |
|---|---|---|
| EBNC | force asynchronous software trap (AST) | 0.19 |
| direct return from interrupt | some processor cycles | |
| using a standard mechanism (see above) | 24.42 | |
A user level library provides access to the mechanism. Have a look at the simple interface:
My supervisors for this work are Christoph Koppe and Frank Bellosa.